Reduction of Latency in an Asynchronous Communication System with Error Correction Capabilities

This paper introduces a new family of error – correction unordered (ECU) codes for global communication, called zero – sum. It is the combination of delay insensitive codes and fault tolerance of error correcting codes. Two important feature of this code are that they are systematic and weighted. For this code, a wide variety of weight assignments is used. Two enhancements are also proposed for zero-sum code. The zero-sum code, it gives error detection for 3-bit errors, or alternatively provides 2-bit detection and 1-bit correction. The zero-sum code, provides heuristic 2-bit correction while still guaranteeing 2-bit detection, under different weight assignments. The outline for this block level system micro architecture is given. In comparison with other ECU codes, the zero-sum code provides better or comparable coding efficiency, with 5.74% 18.18% reduction in average number of wire transitions. Zero-sum code provides 2-bit correction coverage, with 52.92% to 71.16% of all 2-bit errors with only a moderate decrease in number of bits per wire and increase in wire transitions.